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Course Outline
Foundations of RISC-V Architecture and Ecosystem
Understanding the RISC-V ISA Landscape and Industry Adoption
- The philosophy of open ISAs and the standardization efforts led by RISC-V International
- Core mental models for RISC-V: Load-Store architecture, register files, and byte ordering
- Comparative analysis with ARM, x86, and POWER: Evaluating trade-offs for heterogeneous computing
- Assessment of ecosystem maturity involving key players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardized interfaces including the RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and Application Binary Interface (ABI) Compliance
- Overview of the Unprivileged Architecture specification: Control and Status Registers (CSR) map, exception handling, and memory hierarchies
- RV32I/RV64I instruction sets and ABI compliance strategies for cross-platform binary portability
- Memory ordering conventions and barrier instructions essential for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchains
Low-Level Instruction Programming Techniques
- Mastery of base integer (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Strategies for bitness-aware programming targeting both 32-bit and 64-bit RISC-V architectures
- Calling conventions and stack frame management tailored for embedded and real-time software systems
Proficiency with Compiler Toolchains
- Navigating LLVM-based toolchains: Utilizing Clang, LLVM, and Binutils for RISC-V cross-compilation
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimization levels, and profiling-driven code tuning
- Workflows for open-source toolchain development: Building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Systems programming in Rust for RISC-V: Utilizing zero-cost abstractions, unsafe memory management, and bare-metal development techniques
- Navigating No-Std environments: Custom linkers, device driver development, and memory-mapped I/O
- Developing Board Support Packages (BSP) using Zephyr RTOS and Buildroot for RISC-V targets
- Peripheral interfacing including GPIO, I2C, SPI, UART, and DMA controller programming
Power and Performance Optimization Strategies
- Implementing clock gating, power domain management, and low-power mode optimizations
- Conducting cycle-accurate performance analysis using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI (RISC-V SBI Specification): Developing bootloader firmware
- Implementing UEFI/EDK II on RISC-V for modern firmware boot stacks
- Porting Coreboot and U-Boot for RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: Device tree overlays, CPU topology, and interrupt controller (AIA) driver development
- Developing Vendor BSPs and configuring kernels for custom SoC platforms
- Enabling file system support, networking stacks, and containerization features (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Design methodologies for Network-on-Chip (NoC) in RISC-V multi-core processors
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IPs from OpenCores and the ChIPS Framework alongside vendor RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores on FPGA platforms (e.g., BOOM, VexRiscv, PULP)
- Applying SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Utilizing formal verification tools and property-based testing for rigorous RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
Deep Dive into RVV (RISC-V Vector) Extension
- Leveraging vector load/store, vector-fused multiply-add (VFMA), and matrix computation acceleration
- Optimizing SIMD execution through variable-length vector operations (VL, VLEN)
- Utilizing vector mask operations, segment control, and flexible data types for DSP and ML workloads
Designing Custom DSP and Domain-Specific Instructions
- Creating domain-specific accelerators via custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends to support custom instruction generation and code emission
- Defining hardware-software partitioning strategies for integrating accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units (NPUs) featuring systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Applying model quantization techniques (INT8, INT4, FP8) for efficient edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
- Optimizing memory subsystems, including HBM/DDR bandwidth management for ML model weights and activations
- Managing thermal constraints and power budgets for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Building Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments
- Securing the boot chain via root of trust, secure boot, and measured launch attestation
Cryptographic Acceleration Techniques
- Utilizing RISC-V cryptographic extensions (Zk, Zkr, K) for SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Integrating Post-Quantum Cryptography (PQC) for next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking techniques, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastering ISA extension design methodology: Encoding, encoding tables, ABI impact analysis, and submission to RISC-V International specifications
- Designing custom register files with CBAR (Custom Base Address Registers) for efficient operand dispatch
- Modifying instruction pipelining, hazard detection, and pipeline structures to support custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using directed versus constraint-random stimulus generation
- Implementing regression testing frameworks and coverage-driven verification for architectural modifications
- Conducting interoperability testing to ensure custom instructions operate within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors
- Determining ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways using RISC-V, focusing on connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project Execution
- Architecture specification: Designing ISA extensions and core configuration for a defined use case
- RTL implementation in SystemVerilog, including UVM testbenches and formal verification coverage
- Executing FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Customizing Linux BSPs and toolchains for the specific custom RISC-V core
- Deploying AI workloads through NPU integration, model quantization, and performance benchmarking
- Performing security validation via PMP enforcement, secure boot, and cryptographic acceleration benchmarking
- Delivering technical architecture documentation, IP strategy analysis, and cross-functional team presentations
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
