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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The philosophy of an open ISA and the landscape of RISC-V International standardization.
- Understanding the RISC-V mental model: load-store architecture, register files, and byte ordering.
- Comparative analysis with ARM, x86, and POWER architectures to understand trade-offs for heterogeneous computing systems.
- Assessment of ecosystem maturity, including contributions from SiFive, T-Head, Western Digital, and the expanding open-source silicon community.
- Overview of standardized interfaces: RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL).
Memory Models and ABI Compliance
- Unprivileged Architecture specification: CSRs map, exception handling mechanisms, and memory hierarchies.
- RV32I/RV64I instruction sets and Application Binary Interface (ABI) compliance to ensure cross-platform binary portability.
- Memory ordering conventions and barrier instructions essential for multiprocessor systems.
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Fundamentals of base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions.
- Strategies for bitness-aware programming targeting both 32-bit and 64-bit RISC-V platforms.
- Managing calling conventions and stack frames for embedded and real-time software systems.
Compiler Toolchain Proficiency
- Navigating LLVM-based compiler toolchains: utilizing Clang, LLVM, and Binutils for RISC-V cross-compilation.
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments.
- Leveraging compiler intrinsics, optimizing code through various optimization levels, and performing profile-driven tuning.
- Workflows for developing open-source toolchains: building, testing, and packaging custom GCC/Clang toolchains.
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Systems programming in Rust for RISC-V: leveraging zero-cost abstractions, handling unsafe memory management, and developing bare-metal applications.
- Developing in No-Std environments: implementing custom linkers, device drivers, and memory-mapped I/O.
- Utilizing Zephyr RTOS and Buildroot BSP development for RISC-V targets.
- Programming peripheral interfaces: GPIO, I2C, SPI, UART, and DMA controllers.
Power and Performance Optimization
- Optimizing clock gating, power domain management, and low-power modes.
- Analyzing cycle-accurate performance using simulation profilers and hardware performance counters.
- Tuning real-time interrupt latency for safety-critical applications.
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Developing bootloader firmware through OpenSBI, which implements the SBI specification.
- Implementing UEFI/EDK II on RISC-V for modern firmware boot stack development.
- Porting Coreboot and U-Boot to RISC-V single-board computers.
Linux Kernel Integration
- Contributing to the mainline RISC-V kernel: working with device tree overlays, CPU topology, and interrupt controller (AIA) drivers.
- Developing Vendor BSPs and configuring the kernel for custom SoC platforms.
- Implementing file system support, networking stacks, and containerization technologies (Docker, Kubernetes) on RISC-V host systems.
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Design methodologies for Network-on-Chip (NoC) in RISC-V multi-core processors.
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols.
- Integrating open-source IP sources such as OpenCores, the ChIPS Framework, and vendor RTL components.
- Designing bus matrices and integrating memory controllers for DDR, SRAM, eMMC, and PCIe interfaces.
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores on FPGAs (e.g., BOOM, VexRiscv, PULP).
- Applying SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies.
- Using formal verification tools and property-based testing for rigorous RISC-V core validation.
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Exploring vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration.
- Utilizing variable-length vector operations (VL, VLEN) to optimize SIMD execution for specific workloads.
- Employing vector mask operations, segment control, and data type flexibility for DSP and machine learning workloads.
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators using custom extensions and CBAR-based operand interfaces.
- Modifying compiler frontends to generate custom instructions and emit optimized code.
- Strategies for hardware-software partitioning to integrate accelerators into production SoCs.
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units (NPUs): utilizing systolic arrays, tensor cores, and weight compression for on-chip AI acceleration.
- Applying model quantization techniques (INT8, INT4, FP8) for efficient edge deployment on RISC-V.
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets.
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines.
- Optimizing the memory subsystem, including HBM/DDR bandwidth management for ML model weights and activations.
- Balancing thermal and power budgets for edge AI inference systems.
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and securing the Page Table walker.
- Building Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments.
- Establishing boot chain security: defining the root of trust, enabling secure boot, and implementing measured launch attestation.
Cryptographic Acceleration
- Leveraging RISC-V cryptographic extensions (Zk, Zkr, K extensions) for accelerating SHA, AES, RSA, RSA-PSS, and ECC operations.
- Integrating Post-Quantum Cryptography (PQC) for next-generation RISC-V processors.
- Mitigating side-channel attacks through constant-time programming, masking techniques, and hardware random number generators.
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design methodology: covering encoding, encoding tables, ABI impact analysis, and the RISC-V International specification submission process.
- Designing custom register files using CBAR (Custom Base Address Registers) for operand dispatch.
- Optimizing instruction pipelining, hazard detection, and pipeline modifications to support custom extensions.
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using both directed and constraint-random stimulus generation.
- Implementing regression testing frameworks and coverage-driven verification for architectural modifications.
- Conducting interoperability testing to ensure custom instructions function correctly within established ABI constraints.
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for RISC-V automotive processors.
- Determining ASIL-Q classification and developing safety manuals for RISC-V silicon IP.
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection mechanisms for safety-critical RISC-V systems.
Industrial Real-Time and Edge Computing Applications
- Ensuring IEC 61508 SIL compliance and implementing deterministic scheduling on RISC-V multicore platforms.
- Developing Industrial IoT gateways with RISC-V, focusing on connectivity, edge analytics, and OTA firmware update systems.
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: designing ISA extensions and core configurations for a defined use case.
- RTL implementation in SystemVerilog, including UVM testbenches and formal verification coverage.
- FPGA prototyping, boot firmware development, and integrating bare-metal driver stacks.
- Customizing Linux BSP and toolchains for the custom RISC-V core.
- Deploying AI workloads: integrating NPUs, quantizing models, and conducting performance benchmarking.
- Validating security: enforcing PMP, configuring secure boot, and benchmarking cryptographic acceleration.
- Preparing technical architecture documentation, analyzing IP strategy, and presenting to cross-functional teams.
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
